Length: 1/2 day
In this course, you explore the IC6.1.7 VSE XL and VLS XL features and analyze the usability improvements in the constraint-driven flow. You perform hierarchical constraint propagation and analyze the Rapid Analog Prototype (RAP) category in the Circuit Prospector and Module Generator (Modgen).
You then set up and implement a power structure on a given design using VSR, perform Pad Ring Routing using the VSR Power Router, implement Core Ring Routing using the VSR Power Router, create a Block Ring as part of the VSR Auto Routing flow, create Stripes using the Power Router in VSR, perform Cell Rows Routing as part of the Power Routing flow, use Pin-to-Trunk Routing from a macro to the created Power Stripes, generate vias at the intersection of rings, stripes etc, and trim stripes as a part of the Power Routing flow.
After completing this course, you will be able to:
Analyze the constraint-driven flow, Set up and run power routing, Set up and run Virtuoso IPVS (optional)
Software Used in This Course
Virtuoso Layout Suite, Physical Verification System
IC 6.1.7, PVS 14.14
Modules in this Course
Constraint-Driven Flow, Power Routing, Virtuoso Integrated Physical Verification System (Virtuoso IPVS) (Optional)
Layout Design Engineers, Layout CAD Managers, IC Designers, Analog/Mixed-Signal IC Designers, Analog IC Designers, Custom Circuit Designers, Chip Designers
You must have:
Experience with layout design, Knowledge of schematic symbols and MOS devices, A basic knowledge of UNIX/Linux
Or you must have completed the following courses: