Length : 2 days
In this advanced Engineer Explorer course, you learn how real number modeling using SystemVerilog enables high-performance digital-centric, mixed-signal verification. You must have knowledge of Verilog and SystemVerilog languages and experience with Virtuoso® AMS Designer simulator.
You learn how to model analog block operation as discrete real data for high-performance digital-centric, mixed-signal SoC verification. You also examine digital-centric, mixed-signal verification environment called DMS. You explore the advanced capabilities of SystemVerilog – Real Number Models supported by IEEE P1800-2012 LRM like Nettypes and Interconnects. You create SystemVerilog real models and verify their functionality and performance, using the AMS Designer Incisive® platform on the command-line and the AMS Designer Virtuoso design environment.
You examine how to create SystemVerilog2012models with Schematic Model Generator. You apply the Universal Verification Methodology and Mixed-Signal for verification of analog and mixed-signal designs.
After completing this course, you will be able to:
- Identify how real number modeling with SystemVerilog enables high-performance digital-centric, mixed-signal SoC verification
- Create Real Number Models with SystemVerilog real variables and nettypes
- Verify the functionality and performance of SV-RNM models you create with Virtuoso AMS Designer simulator
- Apply the real modeling techniques for creating analog operations and functions
- Identify SV-RNM capabilities supported in IEEE 1800-2012 such as Nettypes (built-in, UDT/UDR) and Interconnects
- Debug the Nettype (UDT/UDR) struct values with Tcl commands and system functions
- Identify how SV port connections are resolved in mixed designs with wildcard notation
- Apply Universal Verification Methodology and Mixed-Signal (UVM-MS) to analog/mixed-signal designs
Software Used in This Course
Incisive Enterprise Simulator XL, Virtuoso AMS Designer Simulator, Digital-Mixed Signal Option to Incisive Enterprise Simulator, Virtuoso Analog Design Environment L, Virtuoso Schematic Editor, Virtuoso Visualization and Analysis XL, SimVision Waveform Display, Virtuoso Behavioral Modeling Option, Virtuoso SMG run time
Incisive 14.2, IC 6.1.6 ISR11
Modules in this Course
Introduction to Real Modeling, SV-RNM Creation and Simulation, SystemVerilog Real Modeling Techniques, SystemVerilog RNM Capabilities, Debug Capabilities for Nettypes, Mixed-Signal Verification Capabilities (optional) , Optional Appendixes, Schematic Model Generator (SMG) , AMS Design and Model Validation (amsDmv) , Connection of SystemVerilog (.*) Ports to AMS, Licensing and Helpful irun Options, Waveform Viewers
Analog/mixed-signal IC designers, Engineers for Analog/mixed-signal IC verification, and Digital modeling and verification
You must have completed the following courses:SystemVerilog for Design and Verification, Mixed Signal Simulations Using AMS Designer