Specman Fundamentals for Block-Level Environment Developers

Length : 5 days

Course Description

In this course, you create an e language reusable block-level verification environment and simulate it with the Xcelium™ simulator and analyze the simulation with the SimVision™ graphical simulation analysis environment.

The course provides an introduction to the e language in the context of the Coverage-Driven Verification (CDV) methodology. You use the standard Universal Verification Methodology (UVM-e) to build a reusable verification environment.

Learning Objectives

After completing this course, you will be able to:

• Explain the need for and nature of the coverage-driven verification methodology
• Implement basic e syntax
• Generate constrained random values
• Define conditional struct subtypes
• Connect to and interact with the DUT
• Check the DUT behavior
• Cover the DUT functionality
• Develop an interface UVC for the Simple Packet Protocol
• Develop a sequence library for stimulus generation
• Develop a module UVC for the SPP router module
• Implement a mechanism to handle reset during verification
• Implement a mechanism to cleanly terminate the simulation

Software Used in This Course

• Xcelium Single-Core
• Integrated Metrics Center

Software Release(s)

XCELIUM1803, MDV1803

Modules in this Course

• Introduction to Coverage-Driven Verification
• e Language Basics
• e Language Basics – Generation
• When Inheritance (AOP Inheritance)
• Connecting to and Interacting with the DUT
• Checking DUT Behavior
• Covering DUT Functionality
• Developing an Interface UVC
• Developing Sequences
• Developing a Module/System UVC
• Handling Reset and End-Of-Test

Audience

• Verification personnel wanting to use the e Functional Verification language and potentially also the e Universal Verification Methodology (e-UVM).

Prerequisites

You must have experience with or knowledge of the following:

• Any Object-Oriented language, such as C++, C#, SystemVerilog class constructs, Java or Python

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