"A very effective training to give a complete picture of the UVM - System Verilog - Advanced Test Bench planning, implementation and debugging process. The time planning to finish labs was excellent. Theory and lab fits very well.”
Johann Steiner, NXP Semiconductors
"Very comprehensive - all you need to get started. Mature and complete course material. Experienced and supportive trainer. Overall good experience with the course, course environment and learning group."
Martin Hoellerer, u-blox
"The course is perfect to get a good understanding and hands-on of building a UVM environment effectively. (…) Very efficient."
Qubo Hu, Atmel
“Very helpful training. I am sure it will prove useful for future work. Good introduction into topics in the lecture and very good labs which are easy to follow but also deepen the understanding."
Stefan Brennsteiner, NXP Semiconductors
"Labs are the best training material. Doing the labs helped me a lot to understand the covered material during the course."
Ivan Santos, Texas Instruments
"Very effective. The labs were well thought of: neither too simple nor too complicated."
Shakeel ur Rehman, Dialog
"Overall I was very satisfied with the course. The learning objectives were clearly met and the hands-on lab exercise helped me very much in achieving this. I would highly recommend this course for all verification engineers. Everything was perfect(...)"
M. Sathyamurthy, IMMS
“I liked the fact that at the end of this course you have the knowledge necessary to start building an UVM environment in SV from zero.(...) I was very pleased about the way that this course evolved and the things learned in here. Thank you!"
Ioan-Bogdan Barzu, Infineon Technologies
"This training UVM was very interesting(…)the trainer is attentive(…)to my questions and problems of design."