- Generates valuable properties in minutes
- Automatically classifies properties
- Can be used at any stage of verification
Saving weeks of tedious, error-prone work, the JasperGold® Behavioral Property Synthesis App automatically deduces and extracts from your register-transfer level (RTL) and simulation traces (FSDB or vcd files) behavioral patterns and time/signal values and expresses them as SystemVerilog Assertion (SVA) properties. Then, the app automatically classifies these properties as assertions or cover properties and also prioritizes them into high-/medium-/low-value categories. As a result, even if you have no knowledge of SVA, you’ll be able to generate many valuable properties quickly.
High-quality assertions and properties are critical to improve verification coverage, expose code and functional coverage holes, and achieve high confidence in the quality of the design. However, writing assertions in standard languages such as SVA or Property Specification Language (PSL) demands specialized knowledge. Even for experts, it can be extremely time-consuming to manually create all the properties required.
The JasperGold Behavioral Property Synthesis App automatically creates a wide range of properties that span many behavioral patterns. In addition to the built-in properties, you can guide the app to create focused libraries of properties with the included BPS Templates capability.
The app helps users enhance verification coverage and identify RTL bugs in several ways:
1. The app may generate a property indicating a specific behavior that you did not anticipate. This may be an indication that the RTL is out of spec.
2. A generated cover can indicate that the testbench has a limited reach and a verification hole is present in the available simulation suite.
3. When the generated assertions are included with the intellectual property (IP) block and inserted into the next higher layer of hierarchy, suddenly firing assertions indicate bugs and/or spec mismatches.