ASI 16.63

Support for the Latest High-Speed Interfaces

DDR4 power-aware signal integrity analysis now includes DQ eye masks. 

USB 3.0 compliance checks now available in Sigrity™ Serial Link Analysis solution.

EMA TimingDesigner Integration for Complete DDR3/DDR4 Timing Closure

Graphical timing spreadsheets show full interface timing relationships.

TimingDesigner and Allegro^® Sigrity Power Aware Signal Integrity—the industry’s most complete timing analysis and timing reporting solution.

SI and PI Base Integration with Sigrity XtractIM Technology

Automatic recognition of package type, component recognition, die bump, and package solder profile, etc.

Batch mode: Sigrity XtractIM™ workspace file (.ximx) is automatically generated and RLCG and SPICE model will be generated automatically.

GUI mode: The workflow setup is automatically completed when launching the  Sigrity XtractIM tool, and model extraction and electrical performance assessment are just a mouse click away.

Allegro Sigrity Integration Improvements

Common waveform and report formats.

Accelerated time-to-analysis as Allegro to Sigrity data conversion is now accomplished through direct read/write.  Allegro constraint generation from the Sigrity SystemSI™ tool.