Companies designing complex semiconductor packages are faced with power integrity (PI) and signal integrity (SI) issues driven by increasing IC speeds and data transmission rates combined with decreases in power-supply voltages and denser, smaller geometries. Stacked die and packages, higher pin counts, and greater electrical performance constraints are making the physical design of semiconductor packages more complex. To address these issues, you need advanced PI and power-aware SI tools that can be used throughout the design process.
Cadence® package design and assessment tools, based on Sigrity™ technology, provide IC package design, analysis, and model extraction capability—and can exchange data with Cadence SiP Layout and Allegro® Package Designer. Assessment capabilities allow you to quickly spot potential signal and power integrity issues. Model extraction capabilities provide unique full package model extraction with accuracy into the multi-gigahertz frequency range
Cadence PI solutions, based on Sigrity technology, provide signoff-level accuracy for AC and DC power analysis of PCBs and IC packages. Each tool seamlessly interfaces with our Allegro PCB and IC packaging physical design solutions.
Cadence power-aware SI tools, based on Sigrity technology, provide signoff-level accurate SI analysis for PCBs and IC packages. Signoff-level SI accuracy of signals with frequency higher than 1GHz must consider the signals and the power/ground network that enables the current return path. Our power-aware SI tools interface seamlessly with our Allegro PCB and IC packaging physical design tools to create a complete power-aware design and SI analysis solution.