- Comprehensive library characterization system including variation modeling and library validation for standard cells and complex I/Os
- Ability to characterize multi-PVT corners in the same run
- Generate statistical libraries in LVF along with nominal using the unified flow
- Critical corner prediction using machine learning algorithms
- Cloud enablement with massive distribution and parallelization algorithms for faster throughput
The Cadence® Liberate™ Trio Characterization Suite is the industry’s first unified library characterization system that brings together characterization, variation modeling, and library validation for standard cells, custom cells, multi-bits, and I/Os. The Liberate Trio Suite includes multi-PVT and unified flows that achieve both accuracy and high-speed performance. Its powerful combination of patented technology for generating and optimizing characterization stimulus and parallel processing capability takes advantage of enterprise-wide compute resources, and it leverages cloud resources for an enormous collection of libraries. The Liberate Trio suite is your one-stop-shop for all aspects of standard cell library characterization and validation.
Unified Library Characterization System
The Liberate Trio suite combines our tested and proven characterization suite with some of the most advanced technology available today in a unified library characterization system.
The Liberate Trio suite provides a new multi-PVT flow to characterize multiple corners in the same run with the resulting libraries maintaining consistency in structure. Vectors and modeling attributes extracted from standard cell circuit analysis are shared among all corners to reduce runtime and ensure the structural symmetry need for static timing analysis (STA) scaling applications. This simplifies the challenge of dealing with an enormous collection of corners across libraries.
Statistical libraries in Liberty Variation Format (LVF) and nominal libraries can now be generated using a unified characterization run that shares statistical and nominal SPICE process models. This flow eliminates the need to merge libraries at the end of a statistical run and the combined characterization run improves performance.
The machine learning algorithms in the Liberate Trio suite enable prediction of critical corners through clustering techniques to determine which corners need to be characterized. The use of machine learning significantly reduces the number of libraries that will need to be characterized while ensuring accuracy using smart interpolation.
Characterization of large libraries that would normally take weeks can now be turned around in days. Thoroughly distributed and massively parallel, our library characterization portfolio has been fully optimized to run on cloud-based servers by making characterization processes. The Liberate Trio suite can be used on leading cloud service providers or a company’s private cloud, and is scalable to over thousands of CPUs.
- Utilizes a single script to characterize all PVT corners in a library using multi-PVT flow
- Statistical and nominal libraries unified in a single characterization run
- Efficient multiprocessing delivers 3X runtime improvements for library sets
- Predicts critical corners using machine learning
- Runtime metrics and results monitoring with a sleek new GUI cockpit
- GlobalFoundries Expert Insights: Aging Analysis for IoT and Automotive Applications
- Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM
- Overview of the Characterization Interface in Liberate Trio Characterization Suite
- Faster Timing Characterization of Analog Macros
- Achieve greater throughput and productivity with Liberate Trio Characterization Suite
- Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization
- Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
- Characterizing 22FDX Library at GLOBALFOUNDRIES
- Library Characterization in the Cloud
Success Story Video (3)
Press Releases (5)
- Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
- Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
- Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations
- Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
- Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production