Filter Results:
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26 Result(s) Found
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A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White PaperTo examine simulation and emulation technologies for a thorough, yet faster functional verification of low-power systems on chip (SoCs), this paper first reviews the fundamental sources and reduction techn...
657 KB
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Texas Instruments and Cadence Verification Success StoryBy combining Palladium XP DPA with Encounter Power System TI achieved close correlation between the architects power estimation and actual silicon power consumption measurements enabling the company to del...
468 KB
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Building Energy-Efficient ICs from the Ground Up White PaperThe design, implementation, and verification tools and flows provided by Cadence address all areas of power management and solve the SoC low-power problem.
344 KB
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UVM methodology based Verification Environment for Imaging IPs/SoCsAbhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in e...
23 Jun 2016
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Developing 4G Wireless Designs with Cadence CPF-Driven Low-Power SolutionAntoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company's next generation 4G wireless designs.
15 Jun 2016
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Augmenting Simulation Via Low-Power Verification Methodologies with EmulationJoin Cadence at 9:00am PST on Wednesday, December 11, 2013, for an informative webinar on two methodologies to migrate low-power verification from simulation to emulation.
21 Jul 2016
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Plan-Driven Low-Power Verification and Debugging at STMicroelectronicsLearn how Mohit Jain from STMicroelectronics applied Cadence Incisive Enterprise Simulator and SimVision debug capabilities for IEEE 1801 / UPF low-power verification by resusing his existing code successf...
22 Aug 2015
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Low Power Verification USING CPF/IEEE 1801 and Application of Formal Verification at Chip LevelShaji Kunjumohamed from Broadcom discusses Low Power Verification using CPF/IEE 1801 and Application OF Formal Verification at Chip Level. The Power Intnet Challenge is that IT touches everything. An over...
22 Mar 2016
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5 Steps to Your First Power Shut-off (PSO) VerificationAdam Sherer and Mickey Rodriguez from Cadence discuss 5 Steps to Your First Power Shut-off (PSO) Verification. Low-Power Verification Raises Silicon Quality and complex conditions open risk for bug escapes...
22 Aug 2015
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6 Must Know Tips to Optimize LPDDR and Wide I/O PerformanceHear Wendy Eisasser discusses 6 Must Know Tips to optimize LPDDR and Wide I/O performance. LPDDR and Wide I/O Compete for Mobile Sockets and which option is best for your next design. A comparison of Memor...
22 Aug 2015
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