UVM Multi-language with e, SystemVerilog, SystemC, C/C++

Cadence's Bryan Sniderman, Adam Sherer discuss UVM-ML Open Architecture. How Multi Language is a strong requirement for verification.  General parts of UVM ML requirements are syrnchronized execution, data passing, unified common utilities, enable reuse of UVC. Demo of multi language use case

上次修改時間: August 22, 2015

持續時間: 20 min