Connecting SystemVerilog Real Numbers and Verilog-AMS Nets

Cadence Webinar: Connecting SystemVerilog Real Numbers and Verilog-AMS Nets. One hour video, from 2016.

Dan Romaine from Cadence discussion on Connecting SystemVerilog Real Numbers and Verilog AMS Nets. What are Mixed signal verification challenges. Many of todays designs include analog or mixed signal blocks. What are Performance Concerns. The trade offs on Modeling abstraction

上次修改時間: August 22, 2015

持續時間: 1h