Reducing Cost, Size of PCBs with Embedded Technologies and Cadence Layout Tools

Dialog Semiconductor faced a potentially daunting challenge: reduce the size and cost of its PCBs via embedded passive devices at the substrate level. The company needed a tool that could help migrate from a two-layer BGA substrate to four layers. Rajesh Aiyandra, package design and simulation team leader at Dialog, explains how Cadence SiP Digital Layout helped deliver a smooth migration, from the change in the number of layers to the change in the via specifications.

上次修改時間: August 18, 2016

持續時間: 3 min