PMC Gains Faster Analog IP Verification with Virtuoso Platform

Engineers at PMC were frustrated with their slow, manual process for verifying analog IP and developing functional models. To automate its processes, the company implemented Cadence® Virtuoso® Schematic Editor and a SystemVerilog testbench. In this video, Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is.

上次修改時間: May 19, 2016

持續時間: 3 min