PMC Gains Faster Analog IP Verification with Virtuoso Platform

Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is when they implemented Cadence Virtuoso Schematic Editor and a SystemVerilog testbench

上次修改時間: February 27, 2019

持續時間: 3 min