Verifying PLLs with SPICE Accuracy in Minutes and Hours

How do you verify  functionality of  phased-lock loops against target performance specifications? You need to consider architecture, impact of advanced technology nodes, device noise, post-layout parasitics, device mismatch, and design integration. Check out our full-day seminar.

上次修改時間: August 26, 2015

持續時間: 4 min