Fast & Efficient Memory Verification and Characterization for Advanced On Chip Variation

Accurate Advanced On-Chip Variation (AOCV) needs the design to be simulated for the random and deterministic process variation. The SRAM design is complex with a lot of logics and functionalities. Creating a simulation setup for SRAM is a time consuming process and doing several Monte Carlo simulations on such a huge netlist to identify the process variation impact requires lot of simulation run time and memory. This video reviews tests performed by Invecas to evaluate traditional methods and the new Cadence Legato Memory Solution to determine the most efficient and accurate process for memory verification and characterization. For more information, visit the Legato Memory Solution page at

上次修改時間: October 2, 2017