Fairchild Semiconductor Eases Floorplanning Challenges of Mixed-Signal Design with Virtuoso Platform

Watch this 1 1/2-minute video to hear how Chris Bennett, ASIC layout engineer at Fairchild Semiconductor, solved a floorplanning challenge in a mixed-signal design using the Cadence® Virtuoso® custom design platform. Routing power to hard macros inside the digital portion of the design was difficult, until the team began using the Virtuoso solution, which also helped assure them that they would meet their EMIR requirements.

上次修改時間: March 24, 2016