Silicon Labs - Power Mode Verification in Mixed-Signal Chips

Subrata Roy, Jayanth Sreedhara from Silicon Labs discuss the problem of verifying a design containing multiple analog ,digital block complexity. This would lead to inefficiency, Low Coverage, Uncertainty. An overview of the Solution is discussed. What is Analog Modeling for Top level Verification

上次修改時間: August 22, 2015

持續時間: 22 min