Silicon Signoff and Verification - 16nm FinFET Challenges and Features

Ruben Molina Product  Marketing Director , Timing Signoff  discusses Silicon Signoff and Verificaiton 16nm FinFE Challenges and Features. Topics include Signoff Drivers-Huge, complex mixed Signal SoC designs, Signoff inefficeiency, 16nm and FinFET

上次修改時間: August 22, 2015

持續時間: 57 min