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In this course, you use the mixed-signal, mixed-language AMS Designer Simulator. You use two different simulation models: the Virtuoso Analog Design Environment graphical-interface use model and the command-line based Incisive® use model that uses the irun executable. In the Virtuoso use model, you run simulations on designs netlisted using the Unified Netlister (UNL) in an AMS UNL flow. You use the Hierarchy Editor to create design configurations and learn the concept of discipline resolution and explore in-depth about using connect rules and associated connect modules for signals crossing domain boundaries. In addition to viewing waveforms in the Virtuoso Visualization and Analysis XL waveform viewer, the SimVision tool is used to view and debug simulation results. You are introduced to behavioral modeling using the Verilog-AMS mixed-signal modeling language.
In the text-based command-line flow, you use different control files and control cards in sync with the amsd block. You run simulations using a single-step irun command. Verilog testbench reuse and bus mapping are discussed. For verifying designs, you learn the interoperability across SystemVerilog, Specman e, SystemC and the AMS Designer. The AMS Designer support for the Common Power Format (CPF) and IEEE 1801 Unified Power Format (UPF) is also discussed. The appendix attached to this course addresses software licensing, and a section on how you can send test cases for evaluation.
After completing this course, you will be able to:
Software Used in This Course
- AMS Designer Simulator from Incisive 14.2-s008
- Virtuoso IC 6.1.6 ISR 11
Modules in this Course
- Core Topics of Virtuoso AMS Designer
- Netlisting with the Unified Netlister
- Creating Configurations with the Hierarchy Editor
- Using AMS Designer in the Virtuoso ADE
- Connect Modules
- SimVision for Debugging Simulations
- Basics of Verilog-AMS Modeling
- Using AMS Designer in a Command-Line Incisive Flow
- Design Verification Using AMS Designer
- Analog/Mixed-Signal IC Designers
- Analog/Mixed-Signal Verification Engineers
- Custom Circuit Designers
- System-Level IC Designers
You must have experience with or knowledge of the following:
- UNIX or Linux OS
Or you must have completed the following courses:
- Analog Modeling with Verilog-A
- Behavioral Modeling with Verilog-AMS
- Real Modeling with Verilog-AMS
Note: Please talk to your training coordinator for details on how you can tailor this course.