Virtuoso Schematic Editor

In the Virtuoso^® Schematic Editor course, you learn to create and edit schematics for use with the suite of Cadence^® simulation and layout tools. You access both the L and XL tool suite capabilities. You place instances, wire schematics, use hierarchical design concepts for multi-level schematics. You then use the Verilog In and SPICE In translators to generate netlists and symbols.

You also create the circuit netlist and run a simulation.

In Schematics XL, you add design rules using the Constraint Editor and Circuit Prospector assistants. In addition, you create inherited connections, and generate layout instances from the schematic.

After completing this course, you will be able to:

• Create schematics, symbols, libraries, and components for use in your designs
• Use bindkeys to increase your efficiency and automate repetitive tasks
• Edit component properties and configurations
• Understand flat and hierarchical schematics
• Create netlists and run simulations
• Run Verilog In and SPICE In to generate netlists and schematic symbols
• Add design constraints in schematics for use in the layout
• Establish inherited connections to allow for variables to establish design properties on hierarchical instances

• Introduction to the Virtuoso Design Environment
• Capturing Design Schematics
• Generating Symbols for the Schematics
• Navigating the Design Hierarchy
• Advanced Schematic Capture Techniques
• Creating Constraints in a Schematic
• Working with Inherited Connections

The Appendix section contains a discussion on using the Power Intent Export Assistant in Schematics XL.