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    • 系统设计与验证
      系统设计与验证概述

      Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.

      系统验证套件 相关产品 A-Z

      工具目录
      • 调试纠错分析
        • Tools
        • Indago Debug Platform
        • Indago Debug Analyzer App
        • Indago Embedded Software Debug App
        • Indago Protocol Debug App
        • SimVision Debug
      • 硬件仿真加速器
        • Tools
        • Palladium Z1 Enterprise Emulation System
        • Palladium XP Series
        • Palladium Dynamic Power Analysis
        • Palladium Hybrid
        • SpeedBridge Adapters
        • Emulation Development Kit
        • Virtual JTAG Debug Interface
        • Accelerated VIP
        • QuickCycles Services
        • VirtualBridge Adapters
      • 形式化验证与静态验证
        • Tools
        • JasperGold Formal Verification Platform (Apps)
        • Assertion-Based Verification IP
        • Incisive Formal Verification Platform
      • FPGA 原型验证
        • Tools
        • Protium S1 FPGA-Based Prototyping Platform
        • Protium FPGA-Based Prototyping
        • SpeedBridge Adapters
      • 验证规划与管理
        • Tools
        • vManager Metric-Driven Signoff Platform
      • 仿真与 Testbench 验证
        • Tools
        • Xcelium Parallel Simulator
        • Incisive Enterprise Simulator
        • Incisive Functional Safety Simulator
        • Incisive Specman Elite
      • 软件驱动验证
        • Tools
        • Perspec System Verifier
        • Indago Embedded Software Debug App
        • Virtual System Platform
      • 验证IP(VIP)
        • Tools
        • Accelerated Verification IP
        • Assertion-Based VIP
        • Verification IP
      • 流程
        • 流程
        • 基于 ARM 设计的验证方案
        • 汽车功能安全性验证
        • 基于覆盖率度量的验证签收
        • 混合信号验证
        • 低功耗验证方法学
    • 数字设计与Signoff
      数字设计与 Signoff 概述

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

      全流程数字解决方案 相关产品 A-Z

      工具目录
      • 模块物理实现
        • Tools
        • Innovus Implementation System
        • First Encounter Design Exploration and Prototyping
        • Virtuoso Digital Implementation
      • 逻辑等效性检查
        • Tools
        • Conformal Equivalence Checker
        • Conformal Smart LEC
      • 形式验证与功能 ECO
        • Tools
        • Conformal ECO Designer
      • 分层设计与布局规划
        • Tools
        • Innovus Implementation System
        • First Encounter Design Exploration and Prototyping
        • Virtuoso Digital Implementation
      • 低功耗验证
        • Tools
        • Conformal Low Power
      • RTL 综合
        • Tools
        • Stratus High-Level Synthesis
        • Genus Synthesis Solution
        • Virtuoso Digital Implementation
      • 功耗分析
        • Tools
        • Joules RTL Power Solution
      • SDC 与 CDC 验证
        • Tools
        • Conformal Constraint Designer
      • 硅签收
        • Tools
        • Pegasus Verification System
        • Quantus Extraction Solution
        • Tempus Timing Signoff Solution
        • Assura Physical Verification
        • Physical Verification System
        • CMP Predictor
        • MaskCompose Reticle and Wafer Synthesis
        • QuickView Signoff Data Analysis
        • LDE Electrical Analyzer
        • Process Proximity
        • Pattern Analysis
        • Litho Physical Analyzer
        • Voltus IC Power Integrity Solution
        • Voltus-Fi Custom Power Integrity Solution
      • 可测性设计
        • Tools
        • Modus DFT Software Solution
      • 流程
        • 流程
        • 3D-IC
        • 先进工艺节点
        • 基于 ARM 的设计
        • 低功耗
        • 混合信号
    • 定制 IC/模拟/ RF 设计
      定制 IC /模拟/ RF 设计概述

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      概述 相关产品 A-Z

      工具目录
      • 特征库提取
        • Tools
        • Liberate Trio Characterization Suite
        • Virtuoso Liberate MX Memory Characterization Solution
        • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
      • 电路设计
        • Tools
        • What's New in Virtuoso
        • Virtuoso Schematic Editor
        • Virtuoso ADE Product Suite
      • 电路仿真
        • Tools
        • Spectre Circuit Simulator
        • Spectre eXtensive Partitioning Simulator
        • Spectre RF Option
        • Spectre AMS Designer
      • 版图设计
        • Tools
        • What's New in Virtuoso
        • Virtuoso Layout Suite
      • 版图验证
        • Tools
        • Virtuoso DFM
        • Physical Verification System
        • Virtuoso Integrated Physical Verification System
      • 流程
        • 流程
        • 电学感知设计(EAD)
        • 先进工艺节点
        • Legato Memory Solution
        • Legato 可靠性解决方案
        • Virtuoso RF Solution
        • Virtuoso System Design Platform
    • IC 封装设计与分析
      IC 封装设计与分析概述

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      概述 相关产品 A-Z

      工具目录
      • IC 封装设计
        • Tools
        • SIP Layout
        • Allegro Package Designer
        • 3D Design Viewer
        • SiP Layout Advanced WLP Option
        • SiP Digital Architect
      • SI/PI 协同分析方案
        • Tools
        • Allegro Sigrity SI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity Package Assessment and Extraction Option
        • Allegro Sigrity PI Base
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI 分析点工具
        • Tools
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity Speed2000
        • Sigrity SystemSI
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity XtractIM
        • Sigrity XcitePI Extraction
      • 跨平台协同设计与分析
        • Tools
        • OrbitIO Interconnect Designer
        • IO-SSO Analysis Suite
      • 流程
        • 流程
        • Cross-Substrate互连
        • IC/封装/PCB协同设计
        • InFO封装技术
        • Sigrity最新技术
        • Virtuoso System Design Platform
        • PDN设计
    • PCB 设计与分析
      PCB 设计与分析概述

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      概述 相关产品 A-Z 生态服务搜索

      工具目录
      • 原理图设计
        • Tools
        • Allegro Design Entry Capture/Capture CIS
        • Allegro Design Publisher
        • Allegro Design Authoring
        • Allegro FPGA System Planner
      • PCB 版图设计
        • Tools
        • Allegro PCB Designer
        • OrCAD PCB Designer
      • 库与设计数据管理
        • Tools
        • Allegro ECAD-MCAD Library Creator
        • Allegro EDM Solution
        • Allegro PCB Librarian
        • Allegro Pulse
      • 模拟/混合信号仿真
        • Tools
        • Allegro PSpice Simulator
        • OrCAD PSpice Designer
      • SI/PI 协同分析方案
        • Tools
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity SI Base
        • Allegro Sigrity PI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI 分析点工具
        • Tools
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity SystemSI
        • Sigrity Speed2000
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity PowerSI 3D EM Extraction Option
      • Allegro最新技术
        • Tools
        • Board Layout
        • Schematic Capture
        • Data Management
      • Sigrity最新技术
        • Tools
        • Sigrity 2018 Release
        • Sigrity Tech Tips
      • 流程
        • 流程
        • Multi-Board PCB System Design
        • 产品创建
        • ECAD MCAD 协同设计
        • Allegro Right First-Time Design
        • IO-SSO分析套件
        • 3D System Design Solutions
        • PDN设计
        • LPDDR4 完整分析方案
        • 功耗感知信号完整性分析
        • 接口感知方法
        • Sigrity串行链路分析
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  • IP
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    • Tensilica 处理器 IP
    • 接口 IP
    • Denali 存储器 IP
    • 模拟 IP
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  • 解决方案
    • 解决方案主页

      全面的解决方案与实现方法

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    • Cadence Cloud
    • 3D-IC 设计
    • 5G Systems and Subsystems
    • 先进工艺节点
    • 航天与国防
    • Arm 解决方案
    • 汽车电子解决方案
    • FPGA Development
    • 低功耗
    • Machine Learning
    • 混合信号
    • 光学
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          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

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        • 24/7 Support - Cadence Online Support

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        • 24/7 Support - Cadence Online Support

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    • Cadence 学术网络
      CAN Overview

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    • 全球培训课程目录
    • Custom IC / Analog / RF Design
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Circuit Design and Simulation
        • Featured Courses
        • Virtuoso ADE Explorer Series
        • Virtuoso ADE Assembler Series
        • Virtuoso ADE Verifier
        • Variation Analysis Using the Virtuoso ADE Assembler
        • Virtuoso Schematic Editor
        • Mixed Signal Simulations Using AMS Designer
        • Spectre Accelerated Parallel Simulator
        • High-Performance Simulation Using Spectre Simulators
        • Additional Courses
      • Electrically-Aware Design
        • Featured Courses
        • High-Performance Simulation Using Spectre Simulators
        • Physical Verification System
        • Virtuoso Analog Design Environment
        • Virtuoso Electrically-Aware Design with Layout-Dependent Effects
        • Virtuoso Schematic Editor
        • Quantus QRC Extraction Series
        • Spectre Accelerated Parallel Simulator
      • Infrastructure
        • Featured Courses
        • Advanced SKILL Language Programming
        • SKILL Development of Parameterized Cells
        • SKILL Language Programming
        • SKILL Language Programming Introduction
        • SKILL Programming for IC Layout Design
      • Layout Design and Verification
        • Featured Courses
        • Virtuoso Layout Pro Series
        • Virtuoso Space-Based Router
        • Virtuoso Floorplanner
        • Quantus QRC Extraction Series
        • Using Virtuoso Constraints Effectively
        • Virtuoso Connectivity-Driven Layout Transition
        • Physical Verification System
      • Library Characterization
        • Featured Courses
        • Cadence Library Characterization and Validation
        • Virtuoso Liberate MX for Memory Characterization
        • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
        • Spectre Accelerated Parallel Simulator
        • Virtuoso ADE Assembler Series
      • Modeling
        • Featured Courses
        • Analog Modeling with Verilog-A
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Mixed Signal Simulations Using AMS Designer
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
        • Mixed-Signal IP and Testbench Reuse
        • Virtuoso ADE Explorer Series
      • RF Design
        • Featured Courses
        • Quantus QRC Transistor-Level T1: Overview and Technology Setup
        • Quantus QRC Transistor-Level T2: Parasitic Extraction
        • Quantus QRC Transistor-Level T3: Extracted View Flows and Advanced Features
        • Spectre Accelerated Parallel Simulator
        • Virtuoso Schematic Editor
        • Spectre RF Analysis using Harmonic Balance
      • Variation Aware Design
        • Featured Courses
        • Virtuoso ADE Assembler S1: Introducing the Assembler Environment
        • Virtuoso ADE Assembler S2: Sweeping Variables, Simulating Corners, and Creating Run Plans
        • Virtuoso ADE Assembler S3: Circuit Checks, Device Asserts, and Reliability Analysis
        • Variation Analysis Using the Virtuoso ADE Assembler
        • Virtuoso Spectre Pro Series
        • High-Performance Simulation Using Spectre Simulators
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Languages and Methodologies
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

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      Tools Categories
      • Assertions
        • Featured Courses
        • Verification with PSL
      • Behavioral Language for AMS Simulation
        • Featured Courses
        • Behavioral Modeling with VHDL-AMS
        • Behavioral Modeling with Verilog-AMS
        • Real Modeling with SystemVerilog
        • Real Modeling with Verilog-AMS
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Training
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog Language and Application
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Digital Design and Signoff
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

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      Tools Categories
      • Block and Hierarchical Implementation
        • Featured Courses
        • Analog-on-Top Mixed-Signal Implementation
        • Encounter Digital Implementation (Hierarchical)
        • Innovus Implementation System (Block)
        • Innovus Implementation System (Hierarchical)
        • Low-Power Flow with Encounter Digital Implementation
        • Additional Courses
      • Equivalence Checking
        • Featured Courses
        • Encounter Conformal ECO
        • Logic Equivalence Checking with Conformal EC
      • Layout Design
        • Featured Courses
        • Virtuoso Digital Implementation
      • Silicon Signoff
        • Featured Courses
        • Voltus Power-Grid Analysis and Signoff
      • Test
        • Featured Courses
        • Encounter Test Jump Start to ATPG
        • Test Synthesis Using Encounter RTL Compiler
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • IC Package Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Cross-Platform Co-Design and Analysis
        • Featured Courses
        • OrbitIO System Planner
        • SiP Layout
      • IC Package Design
        • Featured Courses
        • SiP Layout
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity Package Assessment and Model Extraction
        • Allegro Sigrity SI Foundations
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Allegro Sigrity Package Assessment and Model Extraction
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • PCB Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Analog/Mixed-Signal Simulation
        • Featured Courses
        • Allegro AMS Simulator Advanced Analysis
        • Analog Simulation with PSpice
      • Design Authoring
        • Featured Courses
        • Allegro Design Entry HDL Basics
        • Allegro Design Entry HDL SKILL Programming Language
        • Allegro Design Entry Using OrCAD Capture
        • Allegro System Architect
        • Allegro Team Design Authoring
      • Library and Design Data Management
        • Featured Courses
        • Allegro Design Workbench for Administrators
        • Allegro Design Workbench for Engineers and Designers
        • Allegro Design Workbench for Librarians
        • Allegro PCB Librarian
      • PCB Layout
        • Featured Courses
        • Allegro High-Speed Constraint Management
        • Allegro PCB Editor Basic Techniques
        • Allegro PCB Editor Intermediate Techniques
        • Allegro PCB Router Basics
      • SI/PI Analysis Integrated Solution
        • Featured Courses
        • Allegro Sigrity PI
        • Allegro Sigrity SI Foundations
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • SI/PI Analysis Point Tools
        • Featured Courses
        • Sigrity PowerDC and OptimizePI
        • Sigrity PowerSI for Model Generation and Analysis
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • System Design and Verification
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

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      Tools Categories
      • Emulation and Acceleration
        • Featured Courses
        • Acceleration with Palladium XP
        • In Circuit Emulation with Palladium XP
        • Protium Rapid Prototyping Platform
      • Formal Verification
        • Featured Courses
        • Verification with PSL
      • Planning and Management
        • Featured Courses
        • Foundations of Metric Driven Verification
        • Metric Driven Verification using Incisive vManager
      • Scripting
        • Featured Courses
        • Perl for EDA Engineering
        • Tcl Scripting for EDA
      • Simulation, Testbench and Debug
        • Featured Courses
        • Incisive Functional Safety Simulator
        • Low-Power Simulation with IEEE Std 1801 UPF
      • Specman and UVMe
        • Featured Courses
        • Specman Advanced Training
        • Specman Fundamentals for Block-Level Environment Developers
      • SystemC
        • Featured Courses
        • C++ Language Fundamentals for Design and Verification
        • SystemC Language Fundamentals
        • SystemC Transaction-Level Modeling (TLM 2.0)
      • SystemVerilog and UVM
        • Featured Courses
        • Real Modeling with SystemVerilog
        • SystemVerilog Advanced Register Verification Using UVM
        • SystemVerilog for Design and Verification
        • SystemVerilog for Verification
      • Verilog and VHDL
        • Featured Courses
        • VHDL Language and Application
        • Verification with PSL
        • Verilog Language and Application
        • Verilog for VHDL Users
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

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    • Tensilica Processor IP
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • ConnX DSPs
        • Featured Courses
        • Tensilica ConnX BBE16EP Baseband Engine
        • Tensilica ConnX BBE32EP Baseband Engine
        • Tensilica ConnX BBE64EP Baseband Engine
      • Fusion DSPs
        • Featured Courses
        • Tensilica Fusion F1 DSP
        • Tensilica Fusion G3 DSP
      • HiFi DSPs
        • Featured Courses
        • Tensilica HiFi 2/EP/Mini Audio Engine ISA
        • Tensilica HiFi 3 Audio Engine ISA
      • Tensilica Processors
        • Featured Courses
        • Introduction to System Modeling with Tensilica Processor Cores
        • Tensilica Processor Fundamentals
        • Tensilica Instruction Extension Language and Design
        • Tensilica Xtensa Hardware Verification and EDA
        • Tensilica Xtensa Processor Interfaces
      • Vision DSPs
        • Featured Courses
        • Tensilica Vision P5 DSP
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

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        • Online Training

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  • Perspec System Verifier

Perspec System Verifier

Improves system-level test development by up to 10X

Perspec System Verifier Datasheet

Three Things You Need to Know to Use the Accellera PSS White Paper

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Key Benefits

  • 10X productivity creating SoC tests for complex system scenario verification
  • Correct-by-construction generation of complex concurrent multi-core/multi-threaded tests
  • Verify more corner cases with automatic use-case amplification of state space and timing exploration on the fastest verification engines
  • Easy portability of test intent and test suite to derivative projects

Frustrated by all of the manual effort and time you’re spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you’ll be able to generate 10X more tests 10X faster using this platform solution. In addition, with its integrated debugging capability, you’ll be equipped to reproduce, find, and fix complex SoC-level bugs in order to improve the overall quality of your SoC.

Figure 1: Perspec System Verifier

 

By applying an appropriate level of abstraction, the Perspec System Verifier can meet the growing challenges of validating SoC performance, function, and power.

The platform is portable, supporting reuse across:

  • SoC scope, from IP to the system level, including hardware-aware software
  • Domain experts create the model and describe scenarios, enabling verification and validation engineers to create system-wide tests
  • Generated tests run out of the box on all Cadence verification engines

Using the Perspec System Verifier, you'll benefit from completeness of measurement, with coverage of functionality, flows, and dependencies. You'll also gain knowledge transfer advantages, since the formal, model-based system description supports knowledge sharing between different groups, particularly hardware and software engineers.

Key Features

  • Goal-directed and true constraint solving
  • Multi-platform, multi-language solution leveraging existing standards and proven techniques
  • Automatic use-case amplification of state space and timing exploration on fast verification engines
  • Connect portable stimulus to UVM testbenches for IP and subsystem verification and stimulus portability
  • Coverage and automatic filling capabilities
  • Debug and coverage logging built into the generated C tests to speed both debug and analysis of coverage results
Figure 2: Make complex generated tests easy to understand

Customer Testimonials

  • PSS in Real Life by Texas Instruments
  • Enable Complex CPU System’s Coverage Closure by SW-Driven Stimulus with Structural Coverage Beyond Accelerated Emulator by MediaTek
  • Automated Test Generation to Verify CPU Subsystem for System Level Low Power Management by Perspec by MediaTek
  • Make Stimuli Portable by Using Perspec System Verifier by Texas Instruments
  • Cadence Perspec System Verifier Usage at Sub-System/SoC/Silicon Level for Infineon Aurix Microcontrollers by Infineon
  • Cadence Perspec System Verifier on a Real SoC Verification of a MSP430 Mixed-Signal Microcontroller by Texas Instruments
  • Enabling Verification of Complex System Scenarios Using Perspec System Verifier by STMicroelectronics
  • Automated Test Generation to Verify IP Modified for System Level Power Management by STMicroelectronics
  • Renesas Accelerates IoT Design Using the Cadence Perspec System Verifier by Renesas

REQUEST A DEMO

SoC Test Generation
with Perspec System Verifier

Supporting portable stimulus
specification 1.0 across the
Cadence Verification Suite

LEARN MORE

Mike Bartley, the CEO of Test and Verification Solutions (T&VS), shares his assessment of the emerging Accellera Portable Stimulus Specification.

EEJournal Chalk Talk on Perspec System Verifier

  • Related Products

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    • Incisive Enterprise Simulator
    • Palladium Z1 Enterprise Emulation System
    • Protium S1 FPGA-Based Prototyping Platform
    • Verification IP
    • vManager Metric-Driven Signoff Platform
Videos

Accellera Portable Stimulus Standard Introduction and Demo; Part 3 of 3 - Conclusions

Enabling Verification of Complex System Scenarios Using Perspec System Verifer

Verification Solutions for ARM v7/v8 Based Systems on Chip

Cadence Perspec System Verifier SW Driven SoC Verification Automation

DAC 2017 Report on Accellera Portable Stimulus Specification

AMIQ Eclipse IDE for Perspec Portable Stimulus

A Look at Cadence System Development Tools

Accellera Portable Stimulus Standard Introduction and Demo; Part 1 of 3 – Introduction

Accellera Portable Stimulus Standard Introduction and Demo; Part 2 of 3 – The Demo

Mike Bartley, CEO of T&VS, on Portable Stimulus

Texas Instruments - Using the Perspec Solution

News ReleasesVIEW ALL
  • Cadence Selected as Primary EDA Tool Vendor by GLOBALFOUNDRIES 02/14/2019

  • Cadence Verification Suite Enabled on Arm-Based HPC Datacenters 10/16/2018

  • Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing 10/16/2018

  • Cadence JasperGold Formal Verification Platform Enables Hitachi to Develop Measures for Fault Avoidance to Comply with IEC 61508 Series SIL 4 Requirements 07/05/2018

  • Cadence Perspec System Verifier Supports New Accellera Portable Test and Stimulus Specification 1.0 06/26/2018

BlogsVIEW ALL
Customers

We found that the Perspec technology easily detected issues caused by complex combinations of power mode settings and transitions. The technology can help us dramatically improve productivity and deliver our designs to IoT application developers much faster.

Toshinori Inoshita, Renesas

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With the Perspec approach we get a lot of interesting scenarios “for free” which are difficult to achieve in a directed test. … In case of failures, the scenario viewer helps to understand the intended execution flow.

Thorsten Klose, Infineon

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[It was] easy to generate complex scenarios using [Perspec] Composer drag and drop composition and scenario completion. [The] graphical scenario representation enables collaboration.

Smitha Kaginele and Murthy Hari, Microsemi

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This [Perspec] flow facilitates [absorption of] late design changes rapidly due to automation in the testbench and test case generation.

Vivek Goyal and Vijay Rajan Machingauth, Samsung

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[Perspec] Verification Engineer increased confidence in power sequence support. [This] methodology could be applied to any low-power (LP) verification.

Christophe Lamard, STMicroelectronics

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[Perspec] system model changes can easily regenerate all test cases. Generated stimulus code is very well readable based on templates with the same look and feel as traditional stimuli.

Frank Donner, Texas Instruments

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Perspec improves RTL regression efficiency and quality, ...[and] enables software/hardware co-verification.

Hsuan-Ming Chou, Osmond Yao, and Dennis Hsu, MediaTek

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