Perspec System Verifier

Because it applies an appropriate level of abstraction, Perspec System Verifier can meet the growing challenges of validating SoC performance, function, and power, especially at advanced nodes. The platform is portable, supporting reuse across

• SoC scope, from IP to the system level, including software
• Platforms, including FPGAs, emulators, hardware description language (HDL) simulators, virtual platforms, and silicon
  • Generated tests can be run on all Cadence Verification Suite platforms, including Xcelium^TM Parallel Simulator, Palladium^® Z1 Enterprise Emulation Platform, and Protium^TM S1 FPGA-Based Prototyping Platform
• Users, including architects, hardware developers, verification engineers, and software test engineers

Using Perspec System Verifier, you'll benefit from completeness of measurement, with coverage of functionality, flows, and dependencies. You'll also gain knowledge transfer advantages, since the formal, model-based system description supports knowledge sharing between different groups, particularly hardware and software engineers.

Key Features

• Goal-directed and true constraint solving 
• Multi-platform, multi-language solution leveraging existing standards and proven techniques 
• Coverage and automatic filling capabilities 
• Debug and coverage logging built into the generated C tests to speed both debug and analysis of coverage results