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- Accelerates data collection, management, and analysis of functional verification, with 15X greater scalability than file-based tools
- Automates verification signoff utilizing executable verification plans, while reducing farm utilization by 25%
- Improves design quality using forward-looking metrics and the Metric-Driven Verification methodology for up to 60% reduction in total verification time
The heart of the functional verification process is the verification plan (vPlan), which back-annotates results to a live plan (executable), and defines verification complete. With the vManager platform, you can improve your design quality while benefiting from improved productivity, predictability, controllability, and coordination of your functional verification process. The vManager platform can execute pre-silicon verification testing with Cadence’s Xcelium® Parallel Simulator, JasperGold® Formal Verification Platform, or Palladium Z1® Enterprise Emulation Platform.
The vManager platform can be used to manage the following verification initiatives:
- Formal designer handoff – Utilize assertions, directed scenarios, and formal verification “apps” to get to designer verification faster and easier than simulation, with clear handoff guidelines to the verification team
- RTL digital simulation or acceleration – Verify digital designs from IP to SoC at RTL or gate level, with a comprehensive set of coverage metrics compatible across the Cadence Verification Suite, optimized by the JasperGold platform, and accelerated by the Palladium Z1 platform
- Mixed-signal verification – Real number modeling verification and integration with the Cadence Virtuoso® ADE Verifier accelerates closure of analog or mixed signal designs and provides optimal R&D efficiency
- Low-power verification– Verify all power domains, power-up sequences, and user-driven scenarios starting with CPF or IEEE 1801 definition files, which are visible as verification plans with back-annotated results driven by the vManager platform
- Functional safety verification – Leveraging the same functional verification environment, define failure modes, formally reduce fault space, and automatically execute fault campaigns with traceability to verification and safety
- Software-driven verification – Combine IP from many sources, assemble, and execute integration test scenarios using the Cadence Perspec™ System Verifier’s pre-defined libraries or user-written libraries, changing the focus from RTL metrics to exhaustive use-case coverage and integration verification
- HLS verification – Starting with a high-level design in C/C++ and Stratus™ High-Level Synthesis (HLS), shift left your functional verification efforts to spend less time verifying the model and less time verifying the synthesized RT
- Application software verification – Define application software test scenarios, execute jobs to the Cadence Protium™ S1 Rapid-Prototyping Platform, and measure test results and software code coverage metrics
For RTL designers
The vManager platform lets you easily define and execute your own tests or tests written for you from the verification engineer, and collaborate with your verification team in real time, sharing test cases and doing root cause analysis. Tests can be based on the Xcelium simulator or the JasperGold platform, using the vManager platform to share results.
For functional verification engineers
The vManager platform is the ultimate experience to directly measure functional progress and drill down to bin-level details of the unified coverage database (UNICOV) with the embedded Integrated Metrics Center (IMC). The vManager platform can optimize the farm with ranked tests and smart regressions. Post-execution, the vManager platform will aggregate and merge coverage across engines to see a single result, and intuitively organize verification plans by features to maximize comprehension and reporting visibility.
For functional safety engineers
A single cockpit provides execution to results starting from FMEDA plans, to optimization techniques using formal engines, fault campaign execution of hundreds to thousands of faults in parallel, and traceability and reporting per ISO 26262 guidelines.
For design verification and project managers
The vManager platform provides the automation for aggregating and reporting results, based on real project metrics. Enabled by data congruency across the Cadence Verification Suite, the vManager platform tracks projects and subprojects individually, and aggregates results to a single unified view. It tracks progress, compares to goals, and provides a simplified web-based dashboard for easy viewing and measurement of milestones.
The vManager platform is a true enterprise-class infrastructure that:
- Supports multiple users and user types simultaneously
- Enables configuration of multiple projects using a single infrastructure
- Provides deep integration to execute on a Xcelium, JasperGold, Palladium Z1, or Protium S1 platform
- Aggregates data across multiple sites and enables remote access for remote engineers
- ST Optimizes Verification Across the Globe with the vManager Platform
- Freescale Tracks Thousands of Simulations Before Tapeout for Bug-Free Silicon
- Fast Debug of RTL, Speedy Post Analysis
- Detecting System-Level Corner Cases During Low-Power SoC Verification
- Metric-Driven Verification: A Look at How this Methodology Accelerates Verification Process
- Best Practices in Verification Planning
- Freescale Best Practice in Verification Planning
- Allegro Microsystems Improves Efficiency and Productivity with Incisive vManager Solution
- Incisive vManager Solution - Experience the Difference
- Get Your Weekends Back with Faster Chip Verification Process
Customers Success (4)
Press Releases (8)
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform
- Cadence Announces Next-Generation JasperGold Formal Verification Platform
- Media Alert: Cadence to Showcase System Design and Verification Solutions at DVCon US 2015
- M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification
- Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification
- Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
- Cadence Redefines Verification Planning and Management with Incisive vManager Solution
White Paper (4)
- A Program Manager’s Guide to Successful Integrated Circuit Verification
- SoC Planning, Management, Reporting, Auditing, and Signoff White Paper
- Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools and Techniques White Paper
- Maximizing Verification Effectiveness Using Metric-Driven Verification White Paper
With the Incisive vManager solution and MDV methodology, we significantly improved our large-scale integration verification process by adding automation to capture missing test cases and progress management.
Hiroyuki Shibaki, ASIC Design and Verification Manager, Ricoh
The Incisive vManager solution has been very well accepted by our design and verification teams because it’s really straightforward, intuitive, and easy to use. The Incisive vManager solution helps us with project visibility, which improves our verification productivity.
Mirella Negro Marcigaglia, Verification Manager, STMicroelectronics
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