- Captures more metrics toward verification closure
- Speeds design bring-up time
- Finds bugs missed by standalone formal or testbench simulation
Cadence's Incisive® Enterprise Verifier allows design teams and verification engineers to bring up designs faster, begin bug hunting earlier in the process, gather more metrics toward verification closure by leveraging SVA and PSL covers, and reach bugs deep in the design that can be missed by a standalone simulation or formal analysis approach.
Incisive Enterprise Verifier delivers dual power from tightly integrated formal analysis and simulation engines. It includes Incisive Formal Verifier and Incisive Enterprise Simulator capabilities and adds new engine integration capability. In short, the strengths of each technology are combined and mixed in unique, mutually reinforcing ways to enhance the scalability and effectiveness of the analysis, as well as contribute a wealth of coverage metrics to further accelerate metric-driven SoC and silicon design. With easy set-up, automatic operation for most users, fine-grain control for expert users, and new assertion debug capabilities, Incisive Enterprise Verifier increases return on investment from assertion-based verification. It also provides support for metric-driven SoC and silicon design across the enterprise, with verification planning, regression operations on server farms, consolidated formal and simulation metrics, and multi-core performance improvements.
Additionally, new applications like Code Coverage Unreachability and Assertion-Based Verification IP provide mathematically exhaustive automation of verification processes that can break simulation-only approaches.