Palladium Hybrid

The Cadence^® Palladium^® Hybrid solution integrates a high-performance transaction-level model of the CPU subsystem running on Cadence Virtual System Platform (VSP) with register-transfer level (RTL) for the rest of the SoC running on the Palladium platform. The solution accomplishes this by using Cadence’s exclusive Software Integrator technology to provide cross-domain memory coherency. This solution enables the software to execute at virtual platform speeds (typically between 50 – 100MIPS) and interact with the RTL of the design. The Palladium Hybrid tool also maintains memory coherency between the RTL and virtual domains, delivering 60X improvement in operating system (OS) boot and 10X improvement in post-boot software execution. 

With the Palladium Hybrid solution, you can start software validation up to six months earlier in the design cycle as a result of the fast compile and turnaround times the platform offers. This can typically give you a six-month head start on software validation, which can begin prior to the RTL code freeze where typical FPGA prototyping usually starts. 

Accelerating Embedded Software Development Earlier in Design Cycle

ARM and Cadence have teamed up to accelerate embedded software development earlier in the design cycle. Using Palladium Hybrid technology and ARM^® Fast Models, ARM achieved a 50X faster OS boot-up during the development of its ARM Mali™-T760 GPU.

Compared to the previous emulation-only solution, the combination of Palladium Hybrid technology and ARM Fast Models resulted in an up to 10X speed-up of overall hardware-software testing, reducing ARM’s time from OS boot-up to test from hours to minutes while also improving turnaround time and system quality. This development speed gain boosts the ARM Mali Midgard architecture into a new era of energy efficiency.