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- Reducing ECO loops by up to 3X for faster design closure in digital extraction
- Accurate EM and IR analysis including hierarchical EMIR capabilities for large designs and production proven Self-Heating Effects (SHE) flow
- Achieve up to 3X faster and accurate static timing analysis
- Improve productivity and efficient circuit debugging for faster and smarter design closure in transistor extraction
- Faster simulation runtimes up to 3X with the smallest RC netlist
- Provide accurate parasitics for automotive designs
- Noise analysis and support for LCD/TFT/LED designs
- Accurate characterization and support for standard cells, memory, AMS and interface IP, automotive sensors, and sensitive circuits with Quantus FS (3D field solver)
The Cadence® Quantus™ Extraction Solution is the industry’s most trusted signoff parasitic extraction tool. As a single, unified tool, the Quantus solution supports both cell-level and transistor-level extractions during design implementation and signoff. It’s an integral component of our in-design methodology with both the Innovus™ Implementation System and Virtuoso® platforms.
The Quantus Extraction Solution is the linchpin that allows designers to do more with Rs and Cs on both digital- and transistor-level flows, assuring on-time tapeout. The Quantus solution has multiple touchpoints throughout the full flow before and after signoff. It’s tightly integrated with the Cadence Genus™ Synthesis Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution, Virtuoso ADE Product Suite, Spectre® Accelerated Parallel Simulator (APS) and eXtensive Partitioning Simulator (XPS), Liberate™ Characterization Solution, Legato™ Memory Solution, and Pegasus™ Verification System to allow designers to realize all the benefits listed above.
- Best-in-class accuracy using smart solvers; trusted by customers with multiple tapeouts validated in working silicon
- Massively parallel architecture delivers fastest extraction runtimes with linear scalability to 100s of CPUs
- Fully certified down to 7nm process at all leading foundries
- Quantus FS, the industry's first cloud-ready and massively parallel built-in 3D field solver, provides linear scalability to 1000s of CPUs
Our customers trust the Quantus solution and Quantus FS solution for all types of designs. Our new, breakthrough technology in 3D field solver, the Quantus FS solution eliminates the bottleneck of performance by empowering designers to use a 3D field solver to get the accuracy required for advanced-node designs. Providing linear scalability to 1000s of CPUs and foundry certified down to 7nm, the Quantus FS solution is used for:
- Standard cells, SRAMs, AMS, and interface IP
- Other memories such as DRAM, MRAM, flash, etc.
- Automotive designs such as sensors
- Critical nets and other sensitive designs
After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy.
Sumbal Rafiq, Director of Engineering, AppliedMicro
Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools.
Radhakrishnan Pasirajan, Vice President of Silicon Engineering, Open-Silicon
Using these [Quantus, Tempus, and Tempus ECO] signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.
Dr. Paolo Miliozzi, VP of SoC Technology, MaxLinear
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