- Exhaustively verifies multi-million–gate ASICs and FPGAs several times faster than traditional gate-level simulation
- Decreases the risk of missing critical bugs with independent verification technology
- Enables faster, more accurate bug detection and correction throughout the entire design flow
- Extends equivalence checking capability to complex datapaths and closes the RTL-to-layout verification gap (XL configuration)
- Ensures RTL models perform the same functions as the corresponding transistor circuits implemented on silicon (GXL configuration)
- Advanced adaptive proof algorithms and massively parallel architecture for RTL-to-layout verification dramatically improves runtime (Smart LEC)
As designs continue to get more complicated in order to meet aggressive requirements for power, performance, area, and time to market, the formal verification of the designs continues to be a staple and must-have signoff metric to ensure silicon success.
Cadence® Conformal® Logic Equivalence Checking Solutions provide formal equivalence checking of designs from RTL to P&R.
Conformal Smart LEC
The Conformal Smart Logic Equivalence Checker (LEC) is the next-generation equivalency checking solution. With massively parallel architecture and adaptive proof technology, the Conformal Smart LEC delivers dramatic turnaround time improvements in equivalence checking by over 20X for RTL-to-gate comparisons.
The Conformal Equivalence Checker (EC) offers the industry’s only complete equivalence checking solution for verifying the widest variety of circuits. The Conformal EC-XL configuration provides formal equivalence checking for digital logic, including complex arithmetic logic and datapaths. The Conformal EC-GXL configuration provides formal equivalence checking for custom circuits including memories.