- Massively parallel architectures for handling large FinFET designs and supporting multi-threading on multi-core workstations, as well as distributed processing over networks of computers
- Full-flow FlexColor technology ensures multiple color implementation rules are honored from floorplanning through final signoff
- Concurrent power, performance, and area optimization ensures that all of the benefits of a FinFET process are realized during implementation
Digital design implementation and signoff for 7nm and below
Faster design convergence at 7nm and below requires fully integrated and comprehensive DFM capabilities. It also requires more complex timing models to handle larger designs. The advanced-node design technology in Cadence® InnovusTM Implementation System prevents and corrects harmful lithography hotspots, random defects, on-chip variation, and variation due to chemical-mechanical polishing. Using rule- and model-based in-design analysis (pre-qualified and closely correlated with foundry process simulation), the Innovus Implementation System minimizes risk upfront and prevents unexpected design re-spins and late-stage iterations.
The latest release of the Innovus Implementation System introduces 7nm design implementation and signoff capabilities with correct-by-construction double-patterning support. These double-patterning capabilities span floorplanning, placement, optimization, routing, parasitic extraction, and signoff for timing, power, and physical verification of 7nm and below designs. This correct-by-construction approach to advanced node design ensures faster turnaround time in meeting performance, power, and reliability targets while yielding high-quality results in silicon.
The Innvous Implementation System includes the following steps (as illustrated in Figure 1):
- GigaPlace™ placement engine optimizes cell placement for double-patterning requirements, leading to better area efficiency
- NanoRoute™ Advanced Digital Router with FlexColor technology routes in a correct-by-construction manner; metal is routed to be DRC- and double-patterning–correct using a built-in physical verification engine during all stages of routing
- GigaOpt™ optimization engine considers advanced node characteristics such as correct layer selection for optimal buffering
- Cadence Quantus™ QRC Extraction produces multi-value SPEF files required for litho-biasing support and mask-misalignment modeling
- Tempus™ Timing Solution utilizes min. and max. capacitance values on early and late launch and capture clock paths for setup and hold timing analysis
- Voltus™ IC Power utilizes multi-valued SPEF parasitics for power, IR drop, and AC/DC EM analyses
- Tempus Timing System considers intrinsic waveform effects during signoff timing analysis, including back-miller current effect that acts as an aggressor to affect timing delay
- Cadence Physical Verification System provides in-design signoff for DRC and double-patterning conflict checks