National and Cadence Building a More Efficient Chip Design Flow

In this 4-minute video, George Zafiropoulos, talks about working with Cadence to develop a more efficient chip design flow. Hear what George has to say about what happens when a prototyping platform like Cadence's Palladium environment is connected with National's test environment.

上次修改时间: February 25, 2019

持续时间: 4 min