Analog Behavioral Modeling and Model Generation

Cadence webinar: Analog behavioral modeling and model generation, discussions of Verilog, VHDL, SystemVerilog

Ahmed Elzeftawi and Walter Hartong discuss Analog Behavioral Modeling and Model Generation. Mixed Signal Verification Challenges. Discussion on designs seeing massive increase in digital control, calibration and tuning of analog circuits

上次修改时间: August 22, 2015

持续时间: 58 min