PMC Gains Faster Analog IP Verification with Virtuoso Platform

Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is when they implemented Cadence Virtuoso Schematic Editor and a SystemVerilog testbench

上次修改时间: August 22, 2015

持续时间: 3 min