How do you verify the functionality of your data converters (ADCs and DACs) against target performance specifications? You’ll need to consider your architecture, impact of advanced technology nodes, device noise, post-layout parasitics, device mismatch, and design integration. Take a peek at our full-day seminar featuring technical presentations and hands-on workshops that will help you tackle your verification challenges. You’ll get an overview of data converter design architecture, plus learn best practices, verification plans, methodologies, and techniques using the production-proven Cadence® Spectre® simulation technologies in the Virtuoso® Analog Design Environment (ADE). You’ll gain invaluable insight from our analog IP designers and simulation technology R&D experts on how to verify today’s complex data converter designs more productively and profitably.
上次修改时间: May 10, 2016
持续时间: 4 min