Why Consider SystemVerilog for Synthesizable RTL
Sign up here for our free one-hour webinar with Bhairava Prasad D.!
Tuesday, May 28, 09:30 BST, 10:30 CEST, 11:30 IDT, 14:00 IST, 16:30 CST
Today, most design verification happens with SystemVerilog-based testbenches or UVM—which leads to the misunderstanding that the language is used solely for verification. The fact is, that SystemVerilog has excellent features that can be used for writing synthesizable RTL code.
This webinar—complete with examples—will highlight some of those features.
1. New design constructs and relaxation of datatype rules
2. Specialized procedural blocks
3. Enumerated types and case constructs
6. Q & A