Sigrity 2017 Portfolio Improves Product Creation Time with Enhanced PCB Design and Analysis Methodology and ESD Analysis Workflow
Cadence expanded its Sigrity™ technology portfolio with new capabilities:
- Upgraded power delivery network (PDN) design and analysis flow to accelerate the time to product creation
- New Allegro® PowerTree™ environment for graphically viewing the logical PDN topology. Saved within the PowerTree user interface are source/sink definitions, discrete values, model names, net names, decoupling capacitor values, target impedance constraints, and more.
- Using data stored in the PowerTree environment, design engineers are able to do early analysis (sanity checks) using schematic data to determine if the PDN topology/tree has been properly captured to meet the design criteria.
- During the physical design stage, PowerTree data can be used to automate setup of both AC and DC power integrity analysis. Both power integrity experts and non-experts can benefit from the ability to perform pushbutton analysis. PCB layout designers can utilize the integrated HTML report files to determine exactly what changes need to be made during the design process. Experts will be able to quickly validate any design changes meeting the PDN specified requirements during the validation process.
- New electro-static discharge (ESD) workflow to test the impact of an ESD gun model on a design. Transient-voltage-suppression (TVS) diodes and their ability to clamp the voltage peak are included in the ESD simulation.
- New Serial Link Compliance Kit for PCI Express® (PCIe®) 4.0 to confirm that the 16Gbps interface requirements are met.
- Optimized design flow between IC package designer and characterization engineer
- New cross-probing between electrical performance assessment (EPA) analysis report file and the IC package designer’s editing canvas