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- Best-in-class accuracy using smart solvers; trusted by customers with multiple tapeouts validated in working silicon
- Massively parallel architecture delivers fastest extraction runtimes with linear scalability to 100s of CPUs
- Fully certified down to 7nm process at TSMC and all other leading foundries
- Comprehensive, accurate, and trusted EMIR solution with Cadence Voltus-Fi Solution for all FinFET designs
- Quantus FS, industry's first cloud-ready and massively parallel built-in 3D field solver, provides linear scalability to 1000s of CPUs
The Cadence® Quantus™ QRC Extraction Solution is the industry’s most trusted signoff parasitic extraction tool. As a single, unified tool, the Quantus solution supports both cell-level and transistor-level extractions during design implementation and signoff. It’s an integral component of our in-design methodology with both the Innovus™ Implementation System and Virtuoso® platforms. Furthermore, with its tight integration with the Tempus™ Timing Signoff Solution, it provides the fastest timing signoff turnaround times.
The Quantus solution is built on massively parallel technology and includes an integrated, foundry-certified 3D field solver, Quantus FS. The Quantus solution provides linear scalability to 100s of CPUs in addition to providing the fastest runtimes for single- and multi-corner extraction. It delivers silicon-proven accuracy with 1000s of tapeouts for all process nodes across all foundries
Our customers have trusted the Quantus solution and Quantus FS for all types of designs such as system-on-chip (SoC), custom-digital, image sensors, power MOSFETs, standard-cell, IP, SRAM/bitcell, DRAM and other memories, and custom-analog designs.
The Quantus FS solution eliminates the bottleneck of performance by empowering designers to use a 3D field solver to get the accuracy required for advanced-node designs. The Quantus FS solution provides linear scalability to 1000s of CPUs, is foundry certified down to 7nm. The Quantus FS solution is used for
- Standard cells, SRAMs, AMS, and interface IP
- Other memories such as DRAM, MRAM, flash, etc.
- Automotive designs such as sensors
- Critical nets and other sensitive designs
The Quantus solution provides significant differentiated and silicon-proven functionality for all designs. Some of these features include:
- Hierarchical signal EMIR for digital designs and AoT with Voltus™ IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution
- Up to 5X reduction in turnaround time using Integrated Virtual Metal Fill (IVMF) versus real Metal Fill GDS
- Accurate inductance extraction for both GDS and LEF/DEF with accuracy of less than 10% versus FastHenry, an industry standard tool for golden inductance extraction
- Up to 6X reduction in simulation runtimes using advanced parasitic reduction functionality
- Accurate substrate noise analysis (SNA) functionality with less than 5% accuracy with silicon measurement
- Less than 5% accuracy versus silicon measurements for automotive devices extraction such as PowerMos
After validating the runtimes of Cadence’s Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy.
Sumbal Rafiq, Director of Engineering, AppliedMicro
Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools.
Radhakrishnan Pasirajan, Vice President of Silicon Engineering, Open-Silicon
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