At advanced nodes, there’s a deep conflict between power, performance, and area (PPA) and design turnaround time (TAT). New physical and electrical design challenges emerge, and structures such as FinFETs create new considerations. To remain competitive, you can’t afford to make any tradeoffs to either PPA or TAT. With the features and functions available in Cadence® Innovus™ Implementation System, you won’t have to.
Optimized for industry-leading embedded-processor and other advanced-node designs, Innovus Implementation System is designed to help you achieve your PPA and TAT requirements through the use of solver-based placement technology. As a result, you can achieve up to a 10 to 20% saving in PPA and an up to 10X improvement in TAT. A key component of the system is its NanoRoute™ unified routing and interconnect optimization feature, which helps you quickly achieve concurrent timing, area, signal integrity, and manufacturability convergence during digital implementation.
Bring the Innovus Implementation System into block implementation to achieve faster design closure and better predictability.