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  • Virtuoso Layout Suite

Virtuoso Layout Suite

Accelerated full custom IC layout

Virtuoso Layout Suite GXL Datasheet

Virtuoso Layout Suite XL Datasheet

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Key Benefits

  • Supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels
  • Accelerated performance and productivity from advanced full custom polygon editing through more flexible schematic and constraint-driven assisted full custom layout, to full custom layout automation
  • Enables creation of differentiated custom silicon that is both fast and silicon accurate

As the full custom IC layout suite of the industry-leading Cadence® Virtuoso® platform, the Virtuoso Layout Suite supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels. The enhanced Virtuoso Layout Suite offers accelerated performance and productivity from advanced full custom polygon editing (L) through more flexible schematic-driven and constraint-driven assisted full custom layout (XL), to full custom layout automation (GXL). Seamlessly integrated with the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment, the Virtuoso Layout Suite enables the creation of differentiated custom silicon that is both fast and silicon accurate.

The Virtuoso platform is the industry’s most silicon-proven, comprehensive, custom IC design platform, trusted in taping out thousands of designs each year for more than 25 years.

  • Virtuoso Layout Suite L Datasheet
  • Virtuoso Layout Suite XL Datasheet
  • Virtuoso Layout Suite GXL Datasheet

Features

  • New patented Virtuoso Layout Suite L graphics-rendering engine provides from 10X to 100X accelerated zoom, fit, pan, drag, and redraw performance on large layouts
  • New Virtuoso Layout Suite XL connectivity extractor technology accelerates trace net, probe net, and mark net performance from 10X to 50X on large layouts
  • Patented multi-user Express PCell capability continues to boost design opening performance from 10X to 20X whenever users require PCell evaluation
  • New patented stream-in engine provides accelerated performance from 2X to 20X
  • Virtuoso Layout Suite GXL Space-Based Routing technology automatically enforces process and design rules during interactive and assisted wire and bus editing
  • Virtuoso Layout Suite GXL ModGens (module generators) add a new interactive pattern-manipulation flow, making real-time customization of a high-precision structured layout very visual and simple
  • Virtuoso Layout Suite GXL Space-Based Routing technology at chip levels can deliver high-quality constraint-driven specialty routing to close thousands of nets in minutes, and new structured device-level routing capabilities that can enhance routing productivity by as much as 50%
  • The Virtuoso platform is backed by the largest number of process design kits (PDKs) available from the world’s leading foundries, for process nodes everywhere from mature 0.6µm to advanced 7nm process nodes
Vituoso Layout Suite XL

REQUEST A DEMO

  • Related Products

    • Virtuoso Schematic Editor
    • Virtuoso ADE Product Suite
    • Custom/Analog Advanced Node
    • Virtuoso Layout Suite EAD
    • Virtuoso Space-Based Router
    • Silicon Signoff and Verification
    • Virtuoso Digital Implementation
Resource Library VIEW ALL

Video (13)

  • New Virtuoso Design Platform for Next-Generation Custom IC and System Design
  • PhoeniX Software: Developing First-Time-Right Photonic ICs
  • STMicroelectronics - Improving Productivity with Virtuoso SPD
  • Analog Devices Raises Productivity with ModGen Tools
  • Freescale Accelerates Layout Via Constraint-Driven Design Flow
  • ams Reduces IC Development Effort by Collaborating with Cadence on Layout Productivity
  • Celebrating 25 Years of Virtuoso Innovation
  • Cadence Pattern Matching and DFM Signoff
  • Place-and-Route in Under a Day for Allegro Microsystems
  • Using VSR for Chip Routing on ST smARTpower Technologies
  • Cadence In-Design DFM-LDE Adoption in ST SmartPower PDK
  • Fairchild Semiconductor Eases Floorplanning Challenges of Mixed-Signal Design with Virtuoso Platform

Datasheet (4)

  • Virtuoso Layout Suite GXL Datasheet
  • Virtuoso Layout Suite L Datasheet
  • Virtuoso Layout Suite for Electrically Aware Design Datasheet

White Paper (1)

  • Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment, Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White Paper

Press Releases (8)

  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
  • Cadence Supports New TSMC WoW Advanced Packaging Technology
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
  • Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform
  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
  • Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry

Success Story Video (3)

  • Analog Devices Raises Productivity with ModGen Tools
  • Freescale Accelerates Layout Via Constraint-Driven Design Flow
  • Validating Design Intent and Improving Design Quality at Micron
Videos

PhoeniX Software: Developing First-Time-Right Photonic ICs

Fairchild Semiconductor Eases Floorplanning Challenges of Mixed-Signal Design with Virtuoso Platform

Validating Design Intent and Improving Design Quality at Micron

STMicroelectronics - Improving Productivity with Virtuoso SPD

Place-and-Route in Under a Day for Allegro Microsystems

Using VSR for Chip Routing on ST smARTpower Technologies

Celebrating 25 Years of Virtuoso Innovation

Cadence In-Design DFM-LDE Adoption in ST SmartPower PDK

Analog Devices Automates and Accelerates Layout with Virtuoso Platform

News ReleasesVIEW ALL
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation 10/01/2018

  • Cadence Supports New TSMC WoW Advanced Packaging Technology 05/01/2018

  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process 09/11/2017

  • Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform 04/04/2016

  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow 02/24/2016

BlogsVIEW ALL
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