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- High performance and capacity pre- and post-layout simulation for design and IP characterization at the block and full-chip level, delivering a significant reduction in simulation run time compared to a traditional FastSPICE simulator
- Fully compatible with Spectre simulation platform using a unified simulation front-end
- Comprehensive set of transistor-level static and dynamic circuit checks to identify issues early in the design flow
- Predictable accuracy and runtime tradeoff with speed option to accommodate different needs
- Seamless integration of design and verification in the Virtuoso ADE Product Suite
The Cadence® Spectre® eXtensive Partitioning Simulator (XPS) is a cloud-ready, high-performance transistor-level FastSPICE circuit simulator for pre- and post-layout verification of memories, custom digital, and analog/mixed-signal SoC designs. It delivers the capacity, accuracy, and speed required for verification of modern complex and tightly coupled designs. It uses advanced partitioning techniques to deliver unparalleled performance compared to traditional FastSPICE simulators delivering the needed throughput for design and verification of complex designs.
Reduce Memory Simulation Time from Weeks to Days
Traditional FastSPICE technologies are no longer effective in meeting the verification challenges found at advanced nodes. Spectre XPS complements traditional transistor-level simulation, providing capabilities that address increasing parasitics, low-power circuit structures, variation, and other advanced-node challenges.
With its unique partitioning technology and new FastSPICE algorithm, Spectre XPS supports:
- Higher capacity and up to 10X faster simulation throughput
- Accurate timing and power analysis for advanced-node, low-power embedded memory applications
- Shortened simulation time from weeks to just days
Enhanced Accuracy and Performance for Mixed-Signal Design
The increased complexity and functionality of many mixed-signal designs, such as phase-locked loops (PLL), analog-to-digital converters (ADC), logic, and power management, require new simulation solutions that provide a tradeoff between accuracy and performance. The Spectre XPS mixed-signal capabilities meet this challenge with its unique technologies. After the netlist is read in, the mixed-signal design is partitioned to analog and digital components by Spectre XPS, using either its own technology or a user-controlled option. The analog components are automatically run with Spectre APS, and the digital components with Spectre XPS. The approach ensures analog accuracy and digital performance.
Fully Integrated with the Legato Memory Solution
The Cadence Legato™ Memory Solution provides a one-stop shop for all memory cell design, memory array and compiler verification, and memory characterization needs. Spectre XPS has a flexible use model that can be used as the simulation engine for the solution. During memory characterization, Spectre XPS can simulate the designs with its power network to enable more thorough analysis. During memory characterization, Spectre XPS utilizes its topology recognition to identify its active word/bit lines and applies single-rate and conversation RC reduction algorithm to maintain the utmost accuracy. It meets stringent accuracy requirements for advanced node designs and can be within 2%, 2ps, or 2mV for timing and power simulation.
Spectre XPS also integrates into the Cadence Virtuoso® ADE Product Suite for mixed-signal design, and into the Cadence Virtuoso Liberate™ MX memory characterization tool for SRAM memory characterization.
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