Cadence Webinar 2016: UVM SystemVerilog in a Multi-Language SoC World with Accellera VIP. One hourong video
A discussion on UVM SystemVerilog in a Multi-Language SoC World. Why UVM-ML is Needed and Important. Cadence UVM encompasses many aspects. An overview of examples: reusing SV-UVC in an e Testbench, incorporating SystemC Model in e Testbench. TLM verifcation of SystemC designs.
마지막 수정 날짜: August 22, 2015
지속 시간: 54 min