Leveraging SystemVerilog Real Number Modeling

Cadence Webinar: Leveraging SystemVerilog Real Number Modeling for Mixed-Signal Regressions, 38 minutes from 2016.

Amar Dwarka from Cadence talks about Leveraging SystemVerilog Real Number Modeling for Mixed Signal Regression verification. Virtuoso Platform integrated GUI, integration of simulation engines. Discussion of Key Advangeags of RNM and what included in RNM languages. An explanation of why UDTs UDR

마지막 수정 날짜: August 22, 2015

지속 시간: 38 min