National and Cadence Building a More Efficient Chip Design Flow

In this 4-minute video, George Zafiropoulos, talks about working with Cadence to develop a more efficient chip design flow. Hear what George has to say about what happens when a prototyping platform like Cadence's Palladium environment is connected with National's test environment.

마지막 수정 날짜: August 22, 2015

지속 시간: 4 min