UVM methodology based Verification Environment for Imaging IPs/SoCs

Abhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in earlier and integrated verification.

마지막 수정 날짜: June 23, 2016

지속 시간: 4 min