Nexus Interposers and Cadence Tools Enhance DDRx Designs

Joe Socha  from Nexus is responsible for analyzing tiny PCBs used as interposers between memory devices, target systems. The video talks about how  Cadence Sigrity PowerSI tool enables the team to run what-if cases to gain insights that lead to useful changes in trace widths, impedance

마지막 수정 날짜: August 26, 2015

지속 시간: 3 min