4X Faster Timing Closure on Memory Subsystems with Allegro TimingVision Environment

In this 3-minute video, Bill Munroe, principal PCB designer in the company's Post-Silicon Group, talks about how the technology helped his team achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems.

마지막 수정 날짜: March 18, 2016

지속 시간: 3 min