Saving Routing Resources, Speeding Up Timing Closure at Freescale Semiconductor

How did the engineers improve these processes? Hear Nikhil Murgai, lead design engineer at Freescale Semiconductor, talk about how the team used Cadence Encounter digital implementation tools to save routing resources and speed up the timing closure process.

마지막 수정 날짜: August 22, 2015

지속 시간: 4 min