PMC Gains Faster Analog IP Verification with Virtuoso Platform

Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is when they implemented Cadence Virtuoso Schematic Editor and a SystemVerilog testbench

마지막 수정 날짜: August 22, 2015

지속 시간: 3 min