Verifying PLLs with SPICE Accuracy in Minutes and Hours

How do you verify the functionality of your phased-lock loops (PLLs) against target performance specifications? You’ll need to consider your architecture, impact of advanced technology nodes, device noise, post-layout parasitics, device mismatch, and design integration. Take a peek at our full-day seminar featuring technical presentations and hands-on workshops that will help you tackle your verification challenges. You’ll get an overview of PLL design architecture, plus learn best practices, verification plans, methodologies, and techniques using the production-proven Cadence® Spectre® simulation technologies in the Virtuoso® Analog Design Environment (ADE). You’ll gain invaluable insight from our analog IP designers and simulation technology R&D experts on how to verify today’s complex PLL designs more productively and profitably.

마지막 수정 날짜: May 10, 2016

지속 시간: 4 min