LG Electronics – New Methodology for Full-Chip RFIC Transceiver Co-Verification

Antti Havulinna of LG Electronics presents a new methodology for full-chip RFIC transceiver co-verification, which models the complete IC in full HDL using the Schematic Model Generator (SMG) of the Cadence Virtuoso and reduces simulation times from days to less than an hour.

마지막 수정 날짜: June 14, 2017