SAN JOSE, Calif., 12 Nov 2013
- New power integrity analysis engine with massively parallel execution brings up to 10X faster performance
- New hierarchical architecture supports very large designs up to 1 billion instances
- Tightly integrated with key Cadence tools throughout the design flow, including Cadence Tempus Timing Signoff Solution, for the fastest design closure in the industry
- TSMC certified Voltus technology for its 16nm FinFET process in IR-drop analysis accuracy and EM rule compliance
"As a global leader in embedded processing semiconductor solutions, Freescale is always on the lookout for new design tools that help us innovate and create at the most advanced levels of technology," said Ken Hansen, vice president and chief technology officer at Freescale Semiconductor. "We are teaming early on with Cadence to validate the Voltus technology and we are impressed by its performance gains. This type of enhanced productivity is invaluable to help us meet our time-to-market goals."
Following the May release of Tempus™ Timing Signoff Solution, the Voltus solution marks the second major new product this year from Cadence aimed at speeding design signoff and closure. Using the Voltus solution, Cadence customers can shrink the critical power signoff closure and analysis phase to a minimum through key capabilities including:
- A new massively distributed parallel power integrity analysis engine that delivers a scalable performance gain up to 10X over competing products
- A hierarchical architecture that, coupled with the parallel execution, scales to multiple CPU cores and servers, enabling the analysis of designs of up to a billion instances
- SPICE-accurate solver technology that provides the most accurate power signoff results
- Physically-aware power integrity optimization, such as early rail analysis, de-coupling cap and power gating switches, that improves physical implementation quality and speeds up design closure
- The industry's first unified electrical signoff solution for faster, converged timing and power signoff, when used with Tempus Timing Signoff Solution
- A unique and comprehensive power integrity solution encompassing chip, package and PCB when combined with Encounter® Digital Implementation System and Allegro® Sigrity™ Power Integrity
- Analysis of custom/analog IP in an analog mixed-signal SoC design when integrated with Virtuoso® Power System
- Accurate IC chip power integrity analysis, driven by real-world power stimulus when used with Palladium® Dynamic Power Analysis functionality
The Voltus technology is certified by TSMC for the foundry's 16nm FinFET manufacturing process (Design Rule Manual version 0.5). By meeting TSMC's EDA tool certification criteria, the Voltus solution will enable customers to achieve accurate IR-dropanalysis and EM results. The criteria included meeting accuracy requirements for advanced node design rules, static and dynamic IR-drop analysis and very complex electro-migration rules. Cadence is working with TSMC to complete certification for Design Rule Manual version 1.0
Voltus IC Power Integrity Solution is available now. Cadence will showcase the Voltus capabilities at the Signoff Summit on Nov. 21 at Cadence headquarters in San Jose, Calif. For more information about the Signoff Summit, please click here. For more information about Voltus IC Power Integrity Solution, visit the Cadence website at www.cadence.com/news/voltus.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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