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  • Innovus Implementation System

Innovus Implementation System

先端ノードにおける最高のPPAを最短のTATで実現

Innovus Implementation System データシート

Achieving Optimal PPA and Up to 10X TAT Gain White Paper

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Key Benefits

  • 大規模分散並列処理アーキテクチャーにより、大規模設計に対応、マルチコア・ワークステーション上でマルチスレッディング、ネットワーク・コンピューター上でディストリビューテッド・プロセッシングを活用
  • ソルバーベースの新しい配置テクノロジーGigaPlace™は、スラックを考慮した配置、配線トポロジーを考慮したピンアクセス、20nm以降のDPT等カラーを考慮した配置、最適なパイプライン配置、ベストな配線長、設計密度、PPAを実現
  • 最先端の配線レイヤーを考慮したタイミングおよびパワー最適化エンジンにより、動作時の消費電力とリーク電流を削減

Innovus Implementation Systemは、業界をリードする各種エンベデッド・プロセッサーや16nm, 14nm, 10nmプロセス向けに予め最適化されていますので、立ち上げ期間を短縮でき、設計をより早期に開始することができます。配置、配線、最適化、クロッキングにおける独自の新機能をはじめ、Innovus Implementation Systemは、デザインフロー全体を通して、アップストリームステップとダウンストリームステップからなる新しいアーキテクチャーを搭載しています。このアーキテクチャーを用いることにより、設計のイタレーションが最小化されますので、実行時間が短縮され、高品質な製品をより早く市場に投入することができます。Innovus Implementation Systemを使用することにより、統合され差別化されたシステムを少ないリスクで構築することが可能です。

Implementation systemには様々な重要な機能があります。大規模分散並列処理アーキテクチャーにより、大規模設計に対応、マルチコア・ワークステーション上でマルチスレッディング、ネットワーク・コンピューター上でディストリビューテッド・プロセッシングを活用することができます。

トラックを考慮したタイミングの最適化を特長とする次世代のスラック・ドリブン配線により、設計早期よりシグナル・インテグリティを考慮し、実配線後との相関性を改善します。Implementation Systemは、電気的な最適化と物理的な最適化の並列実行に対応するフルフロー・マルチ・オブジェクティブテクノロジーを含みます。また、論理合成からフィジカル・インプリメンテーション、サインオフに至るフロー全体でカスタマイズ可能な共通のユーザーインターフェイス(UI)を搭載し、ロバストな可視化およびレポート機能により、設計の効率と生産性が向上します。

Innovus Implementation Systemは、ケイデンスのサインオフ・ツールであるTempus™ static timing analysis,  Quantus™  extraction, Voltus™ power integrity technologiesを統合しています。この統合により、フィジカル・インプリメンテーションの早期に寄生、タイミング、シグナル・インテグリティ、パワーインテグリティの課題を正確にモデル化することができますので、これらの電気的なメトリクスにおいてより迅速な収束を得ることができ、より速いデザイン・クロージャーを実現します。

Anirudh Devgan reviews the top three benefits of the Innovus Implementation System

  • Related Products

    • First Encounter Design Exploration and Prototyping
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    • Quantus Extraction Solution
    • Voltus IC Power Integrity Solution
    • Tempus Timing Signoff Solution
  • Related Solutions

    • Mixed-Signal Implementation
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Customers

Our products enable the reception of broadband data and video content, requiring high levels of performance, small silicon die-size, and rapid time to market. Innovus Implementation System has provided us with unprecedented full-flow speed-up, so we can deliver reliable designs to market faster.

Dr. Paolo Miliozzi, Senior Director, SOC Technology and Physical Design, MaxLinear

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We've tested the full Innovus Implementation System flow on some of our most congestion-challenged 28nm networking IP blocks and have achieved excellent results while seeing significant throughput improvements. The new Cadence solution has enabled us to resolve our most difficult timing requirements…

Fares Bagh, Vice President, Hardware and Architecture Engineering in Freescale's Digital Networking Group

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Our next system-on-chip (SoC) projects will be on a 16nm process, and the Innovus Implementation System can enable much larger blocks than previously possible, decreasing area and top-level complexity.

Debashis Basu, ‎SVP Engineering, Silicon and Systems Engineering, Juniper Networks

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Innovus Implementation System provided us with substantial gains in quality of results and speed-up for our most challenging design.

Tatsuji Kagatani, Dept. Manager, Design Automation Dept., Elemental Technology Development Division at Renesas System Design Co., Ltd.

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At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets. We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement…

Noel Hurley, General Manager, CPU Group, ARM

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The Innovus Implementation System significantly improved the runtime on a critical multi-million-cell IP core compared to our previous solution. With runtimes improved to deliver more than a million cells per day of implementation throughput, we can confidently drive our aggressive schedules…

Robin Lu, Vice President of ASIC, Spreadtrum Communications

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