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- Enables ultra-fast throughput to complete library validation overnight on a small number of multi-core computers
- For library providers, assures the library quality before the library is shipped
- For library users, allows cross-checking of the incoming library and provides a clear understanding of the impact of any changes due to revisions of extracted cell netlists or process models
- Ensures coverage of all function descriptions, necessary timing, noise, power, leakage arcs, and states in the input library directly against the transistor-level circuit
- TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements
The Cadence® Virtuoso® Liberate™ LV library validation solution provides a comprehensive library validation system including function equivalence and data consistency checking, revision analysis, and correlation with various electrical analysis tools for timing, noise, and power.
The cloud-ready Liberate LV solution provides a collection of utilities for validating libraries, including functional equivalence checking, data consistency checking, revision analysis, and correlation with various electrical analysis tools for timing, noise, and power. The Liberate LV solution provides the means to validate and verify the final library to ensure consistency, completeness, and accuracy.
- Read article on “Library "Safe Margins"—Are They Really Saving Your Design?”
Automotive TCL1 Certified for ISO 26262
The industry’s first digital implementation and signoff flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The Virtuoso Liberate Characterization Solution is part of the flow covering RTL-to-GDSII implementation and signoff. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.
- Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM
- Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization
- Faster Timing Characterization of Analog Macros
- Characterizing 22FDX Library at GLOBALFOUNDRIES
- Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
- Ultra-Low Voltage SRAM: Addressing the Characterization Challenge
- Liberate MX Product Demonstration
Success Story Video (3)
Press Releases (1)
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